This invention relates to integrated circuit packages. More particularly, the invention relates to a method of manufacturing an integrated circuit carrier for an integrated circuit package.
Due to the ever-increasing number of connections (pincount) of integrated circuits, the use of ball grid array packages to connect integrated circuits to printed circuit boards is increasing. This facilitates the redistribution of a very fine pitch of flip-chip bump array of the integrated circuit to a much larger pitch ball grid array for attachment to the printed circuit board (PCB).
The carrier is often referred to as an interposer and can be fabricated from different materials such as ceramic, or a plastics material such as bismaleimide triazine. (BT).
The carrier also functions as a heat sink by removing thermal energy from the integrated circuit by thermal conduction. Accordingly, the carrier is subjected to thermal strains.
In addition, an electronic package assembly comprising the integrated circuit, the carrier and the PCB has a number of different materials with different mechanical properties. Complex thermal stresses can occur inside the package during operation due to non-uniform temperature distributions, geometry, material construction and thermal expansion mismatches.
Typically, these days the integrated circuit is electrically connected to the carrier by a ball grid array of gold or solder bumps. Similarly, the carrier is electrically connected to the PCB by a further, larger ball grid array of solder balls. The thermo-mechanical stresses are typically severest at the solder ball interfaces between the PCB and the carrier. This can result in shearing of the solder ball connection. The problem is amplified by an increase in edge length of the carrier because of an increase in the thermal strain differences between the PCB and the carrier. An increase in edge length of the carrier is typically associated with an increase in the number of integrated circuit connections and solder balls.
Current ball grid array design is, presently, at the limit of reliability for typical integrated circuit pin counts.
Typically, a solder ball has a peak elastic shear strain value of around 0.08%. Computational experiments done by the applicant using a 500 micron thick solid Silicon carrier, 500 micron diameter solder balls at 1 millimeter pitch, a 700 micron thick PCB and a 16 millimeter side silicon chip indicated a peak shear strain value of 1.476% in the outermost ball of the package which is far above the plastic yield value of the solder ball.
This result is to be expected as the balls at the outermost edge of the package experience the greatest amount of translational shear.
As indicated in the publication of the Assembly and Packaging Section of the International Technology Road Map for Semiconductors,xe2x80x941999 Edition (copy attached), the most recent edition available at the time of filing the present application, in Table 59a at page 217, a pin count of a high performance integrated circuit has of the order of 1800 pins. The technology requirements in the near term, i.e. until the year 2005 indicate that, for high performance integrated circuits, a pin count exceeding 3,000 will be required for which, as the table indicates, there is, to date, no known solution. Similarly, in Table 59b of that publication, at page 219, in the longer term, until approximately the year 2014, a pin count for high performance integrated circuit packages of the order of 9,000 will be required. Again, as indicated in the table, there is no known solution for this type of package.
These aspects are the focus of the present invention.
According to the invention there is provided a method of manufacturing an integrated circuit carrier the method including the steps of
providing a substrate;
demarcating at least one receiving zone for an integrated circuit on the substrate and a plurality of island-defining portions arranged about said at least one receiving zone; and
creating rigidity-reducing arrangements between neighboring island-defining portions by removing material from the substrate.
The method may include forming electrical contacts in said at least one receiving zone and forming an electrical terminal in each island-defining portion, each electrical terminal being electrically connected via a track of a circuitry layer to one of the electrical contacts.
Accordingly, the method may include forming the circuitry layer on a surface of the substrate by depositing a metal layer on the substrate. Then, the method may include etching the metal layer to form tracks.
The method may include demarcating said at least one receiving zone and the island-defining portions by means of a mask applied to a surface of the substrate.
The method may then include removing the material of the substrate to create the rigidity-reducing arrangements by etching through the substrate after the exposure of the substrate, carrying the mask, to light.
Preferably, the method includes forming the rigidity-reducing arrangements by means of a re-entrant etch to improve heat sink capabilities of the carrier.
The method may include creating secondary rigidity-reducing arrangements between each of those island-defining portions bordering said at least one receiving zone and said at least one receiving zone. Once again, the method may include creating the secondary rigidity-reducing arrangements by etching through the substrate.
The method may include forming the substrate from a wafer from undoped silicon having an insulating layer. The insulating layer may be used as a hard mask for the etch.
The method may include demarcating said at least one receiving zone by forming a recess in the substrate. The recess may be demarcated by etching the substrate.
Instead, the method may include demarcating said at least one receiving zone by forming a passage through the substrate, a region of the substrate surrounding the passage carrying the electrical contacts. Once again, the passage may be formed by etching the substrate.